74HCT173D Datasheet | Nexperia

description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs. A HIGH on either output enable pin causes the outputs to assume a high-impedance OFF-state. Operation of the output enable inputs does not affect the state of the flip-flops. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits - plies with JEDEC standard no. 7A - Input levels: - For 74HC173: CMOS level - For 74HCT173: TTL level - Gated input enable for hold (do nothing) mode - Gated output enable control mode - Edge-triggered D-type register - Asynchronous master reset - ESD protection: - HBM JESD22-A114F exceeds 2000 V - MM JESD22-A115-A exceeds 200 V - Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC173D -40 °C to +125 °C 74HCT173D 74HC173PW -40 °C to +125 °C Name SO16 TSSOP16 Description plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT403-1 Nexperia 74HC173; 74HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state 4. Functional diagram 7 CP 14 D0 Q0 3 13 D1 FF1 Q1 4 12 D2 to Q2 5 FF4 11 D3 Q3 6 9 E1 10 E2 15 MR 1 OE1 2 OE2...