Datasheet4U Logo Datasheet4U.com

74HCT173 - Quad D-type flip-flop

This page provides the datasheet information for the 74HCT173, a member of the 74HC173 Quad D-type flip-flop family.

Datasheet Summary

Description

The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop.

Features

  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC173: CMOS level.
  • For 74HCT173: TTL level.
  • Gated input enable for hold (do nothing) mode.
  • Gated output enable control mode.
  • Edge-triggered D-type register.
  • Asynchronous master reset.
  • ESD protection:.
  • HBM JESD22-A114F exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200 V.
  • Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering.

📥 Download Datasheet

Datasheet preview – 74HCT173

Datasheet Details

Part number 74HCT173
Manufacturer nexperia
File Size 270.44 KB
Description Quad D-type flip-flop
Datasheet download datasheet 74HCT173 Datasheet
Additional preview pages of the 74HCT173 datasheet.

📁 Similar Datasheet

  • 74HCT173 - Quad D-type flip-flop (Philips)
  • 74HCT173 - Quad D-Type Flip-Flop (Texas Instruments)
  • 74HCT174 - Hex D-type flip-flop (Philips)
  • 74HCT175 - Quad D-type flip-flop (Philips)
  • 74HCT10 - Triple 3-input NAND gate (Philips)
  • 74HCT107 - Dual JK flip-flop (Philips)
  • 74HCT109 - Dual JK flip-flop (Philips)
  • 74HCT11 - Triple 3-input AND gate (Philips)
  • 74HCT11 - Triple 3-input AND gate (NXP)
  • 74HCT112 - Dual JK flip-flop (Philips)
Other Datasheets by nexperia

Full PDF Text Transcription

Click to expand full text
74HC173; 74HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state Rev. 4 — 25 January 2021 Product data sheet 1. General description The 74HC173; 74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition. A HIGH on either input enable will cause the device to go into a hold mode, outputs hold their previous state independently of clock and data inputs. A HIGH on MR forces the outputs LOW independently of clock and data inputs.
Published: |