Nexperia 74HCT173
74HCT173 is a quad positive-edge triggered D-type flip-flop. The device features clock (CP), master reset (MR), two input enable (E1, E2) and two output enable (OE1, OE2) inputs. When the input enables are LOW, the outputs Qn will assume the state of their corresponding Dn inputs that meet the set-up and hold time requirements on the LOW-to-HIGH clock (CP) transition.| Part No. | 74HCT173 |
|---|---|
| Datasheet | 74HCT173 Download |
| Manufacturer |  Nexperia |
| Description | Quad D-type flip-flop |
| Buy | Stock & Price |
FEATURES AND BENEFITS
● Complies with JEDEC standard no. 7A● Input levels:
● For 74HC173: CMOS level
● For 74HCT173: TTL level
● Gated input enable for hold (do nothing) mode
● Gated output enable control mode
● Edge-triggered D-type register
● Asynchronous master reset
● ESD protection:
● HBM JESD22-A114F exceeds 2000 V
● MM JESD22-A115-A exceeds 200 V
● Specified from -40 °C to +85 °C and -40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Temperature range 74HC173D -40 °C to +125 °C 74HCT173D 74HC173PW -40 °C to +125 °C Name SO16 TSSOP16
DESCRIPTION
plastic small outline package; 16 leads; body width 3.9 mm plastic thin shrink small outline package; 16 leads; body width 4.4 mm Version SOT109-1 SOT403-1 Nexperia 74HC173; 74HCT173 Quad D-type flip-flop; positive-edge trigger; 3-state 4. Functional diagram 7 CP 14 D0 Q0 3 13 D1 FF1 Q1 4 12 D2 to Q2 5 FF4 11 D3 Q3 6 9 E1 10 E2 15 MR 1 OE1 2 OE2 aaa-024783 Fig. 1. Functional diagram D0 14 13 12 11 9 E1 D0 D1 D2 D3 10 E2 7 CP 1 OE1 2 OE2 MR Q0 Q1 Q2 Q3 9 & 10 C1 7 1 & 2 EN 15 R 14 1D 3 13 4 12 5 15 3 456 aaa-024784 11 6 aaa-024785 Fig.
