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74HCT297 - Digital phase-locked-loop filter

Datasheet Summary

Description

The 74HC/HCT297 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard no.

7A.

Features

  • Digital design avoids analog compensation errors.
  • Easily cascadable for higher order loops.
  • Useful frequency range:.
  • DC to 55 MHz typical (K-clock).
  • DC to 35 MHz typical (I/D-clock).
  • Dynamically variable bandwidth.
  • Very narrow bandwidth attainable.
  • Power-on reset.
  • Output capability: standard/bus driver.
  • ICC category: MSI.

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Datasheet preview – 74HCT297

Datasheet Details

Part number 74HCT297
Manufacturer Philips
File Size 101.43 KB
Description Digital phase-locked-loop filter
Datasheet download datasheet 74HCT297 Datasheet
Additional preview pages of the 74HCT297 datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06 74HC/HCT/HCU/HCMOS Logic Package Information • The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT297 Digital phase-locked-loop filter Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Digital phase-locked-loop filter FEATURES • Digital design avoids analog compensation errors • Easily cascadable for higher order loops • Useful frequency range: – DC to 55 MHz typical (K-clock) – DC to 35 MHz typical (I/D-clock) • Dynamically variable bandwidth • Very narrow bandwidth attainable • Power-on reset • Output capability: standard/bus driver • ICC category: MSI GENERAL DES
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