Philips 74HCT4024
The 74HC/HCT4024 are high-speed Si-gate CMOS devices and are pin compatible with the “4024” of the “4000B” series. They are specified in compliance with JEDEC standard no. The 74HC/HCT4024 are 7-stage binary ripple counters with a clock input (CP), an overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (Q0 to Q6).| Part No. | 74HCT4024 |
|---|---|
| Datasheet | 74HCT4024 Download |
| Manufacturer |  Philips |
| Description | 7-stage binary ripple counter |
| Buy | Stock & Price |
FEATURES
● Output capability: standard● ICC category: MSI
GENERAL DESCRIPTION
7A. The counter advances on the HIGH-to-LOW transition of CP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state of CP. Each counter stage is a static toggle flip-flop. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.APPLICATIONS
● Frequency dividing circuits● Time delay circuits QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns SYMBOL PARAMETER CONDITIONS tPHL/ tPLH fmax CI CPD propagation delay CP to Q0 maximum clock frequency input capacitance power dissipation capacitance per package CL = 15 pF; VCC = 5 V notes 1 and 2 Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2.
