FEATURES
s Low-power dissipation s Complies with JEDEC standard no. 7A s ESD protection: x HBM EIA/JESD22-A114-B exceeds 2000 V x MM EIA/JESD22-A115-A exceeds 200 V. s Multiple package options s Specified from −40 °C to +80 °C and from −40 °C to +125 °C. Philips Semiconductors 74HC73 Dual JK flip-flop with reset; negative-edge trigger 3. Quick reference data Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns. Symbol tPHL, tPLH Parameter propagation delay nCP to nQ nCP to nQ nR to nQ, nQ fmax CI CPD [1] Conditions CL = 15 pF; VCC = 5 V Min - Typ 16 16 15 77 3.5 30 Max - Unit ns ns ns MHz pF pF maximum clock frequency input capacitance power dissipation capacitance per flip-flop CL = 15 pF; VCC = 5 V - VI = GND to VCC [1] - CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; ∑(CL × VCC2 × fo) = sum of outputs.
Philips
