74HCT73 Overview
The 74HC73 is a high-speed Si-gate CMOS device and is pin patible with low-power Schottky TTL (LSTTL). The 74HC73 is specified in pliance with JEDEC standard no. The 74HC is a dual negative-edge triggered JK flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs;.
74HCT73 Key Features
- Typ 16 16 15 77 3.5 30
- Unit ns ns ns MHz pF pF
- VI = GND to VCC
- CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + ∑(CL × VCC2 × fo) where: f
- 12 November 2004