Philips 74HCT75
The 74HC/HCT75 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. The two latches are simultaneously controlled by one of two active HIGH enable inputs (LE1-2 and LE3-4).| Part No. | 74HCT75 |
|---|---|
| Datasheet | 74HCT75 Download |
| Manufacturer |  Philips |
| Description | Quad bistable transparent latch |
| Buy | Stock & Price |
FEATURES
● Complementary Q and Q outputs● VCC and GND on the centre pins
● Output capability: standard
● ICC category: MSI
GENERAL DESCRIPTION
7A. 74HC/HCT75 The 74HC/HCT75 have four bistable latches. When LEn-n is HIGH, the data enters the latches and appears at the nQ outputs. The nQ outputs follow the data inputs (nD) as long as LEn-n is HIGH (transparent). The data on the nD inputs one set-up time prior to the HIGH-to-LOW transition of the LEn-n will be stored in the latches. The latched outputs remain stable as long as the LEn-n is LOW. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nD to nQ, nQ LEn-n to nQ, nQ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz fo = output frequency in MHz ∑ (CL × VCC2 × fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the conditi...
