Philips 74LV107
The 74LV107 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT107. The 74LV107 is a dual negative-edge triggered JK-type flip-flop featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs. The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.| Part No. | 74LV107 |
|---|---|
| Datasheet | 74LV107 Download |
| Manufacturer |  Philips |
| Description | Dual JK flip-flop |
| Buy | Stock & Price |
FEATURES
● Wide operating: 1.0 to 5.5 V● Optimized for low voltage applications: 1.0 to 3.6 V
● Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
● Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
● Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
● Output capability: standard
● ICC category: flip-flops QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr = tf ≤ 2.5 ns SYMBOL PARAMETER Propagation delay nCP to nQ nCP to nQ nR to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25°C Tamb = 25°C
DESCRIPTION
The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. CONDITIONS TYPICAL 15 15 15 77 3.5 UNIT tPHL/tPLH fmax CI CPD CL = 15 pF; VCC = 3.3 V ns MHz pF pF VI = GND to VCC1 30 NOTE: 1. CPD is used to dete...
