Philips 74LV109
The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109. The 74LV109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input.| Part No. | 74LV109 |
|---|---|
| Datasheet | 74LV109 Download |
| Manufacturer |  Philips |
| Description | Dual JK flip-flop |
| Buy | Stock & Price |
FEATURES
● Optimized for low voltage applications: 1.0 to 3.6 V● Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
● Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V,
● Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V,
● Output capability: standard
● ICC category: flip-flops Tamb = 25°C Tamb = 25°C
DESCRIPTION
The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The JK design allows operation as a D-type flip-flop by tying the J and K inputs together. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. QUICK REFERENCE DATA GND = 0 V; Tamb = 25°C; tr =tf ≤ 2.5 ns SYMBOL tPHL/tPLH fmax CI CPD PARAMETER Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop VI = GND to VCC 1 CONDITIONS TYPICAL 14 12 12 77 3.5 20 UNIT ns MHz pF pF CL = 15 pF; VCC = 3.3 V NOTE: 1.
