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74LV109 - Dual JK flip-flop

General Description

The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109.

The 74LV109 is a dual positive-edge triggered JK-type flip-flop featuring individual J, K inputs, clock (CP) inputs, set (SD) and reset (RD) inputs; also complementary Q and Q outputs.

Key Features

  • Optimized for low voltage.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74LV109 Dual JK flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1997 Jun 06 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Dual JK flip-flop with set and reset; positive-edge trigger 74LV109 FEATURES • Optimized for low voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, • Output capability: standard • ICC category: flip-flops Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV109 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC/HCT109.