SAA2022 Datasheet | Philips Semiconductors

FEATURES - Integrated error correction encoder/decoder function with Digital pact Cassette (DCC) optimized algorithms - Control of capstan servo during recording and after recording by microcontroller - Frequency and phase regulation of capstan servo during playback - Choice of two Dynamic Random Access Memory (DRAM) types operating in page mode - Scratch pad RAM area available to microcontroller in system DRAM - Low power standby mode - I2S interface - Microcontroller interface for high-speed transfer burst rates up to 170 kbytes per second - SYSINFO and AUXILIARY data flags on microcontroller interface - Protection against invalid AUXILIARY data - +4 V operating voltage capability. ORDERING INFORMATION EXTENDED TYPE NUMBER SAA2022GP Note 1. PACKAGE PINS 64 PIN POSITION QFP (1) GENERAL DESCRIPTION Performing the tape formatting and error correction functions for DCC applications, the SAA2022 can be used in conjunction with the PASC (SAA2002/SAA2012), tape equalization (SAA2032), read amplifier (TDA1317 or TDA1318) and write amplifier (TDA1316 or TDA1319) circuits to implement a full signal processing system. MATERIAL plastic CODE SOT208A When using reflow soldering it is remended that the Dry Packing instructions in the “Quality Reference Pocketbook” are followed. The pocketbook can be ordered using the code 9398 510 34011. February 1994 February 1994 3 BLOCK DIAGRAM Philips Semiconductors Tape formatting and error correction for the DCC system V DD1 LTCLK LTEN LTCNT1 LTCNT0 PINI SBEF SBDA SBCL SBWS SBMCLK TCH0 - 7, TAUX 5 6 3 4 49 57 62 61 60 56 33- 41 43 V DD2 8 V DD3 27 V DD4 59 2 29 28 32 TAPE INPUT BUFFER TAPE OUTPUT BUFFER SB - I 2 S INTERFACE MICROCONTROLLER INTERFACE 50 51 LTDATA WDATA WCLOCK PINO1 PINO2 PINO3 ERROR CORRECTION CODER 9 15 17- 25 RASN CASN A0- 8 CLOCK GENERATOR CONTROL DRAM INTERFACE 11- 14 D0- 3 10 16 WEN OEN LTREF URDA SBDIR SPEED SPDF RESET PWRDWN...