HYB18T1G800BC - 1-Gbit Double-Data-Rate-Two SDRAM

This page provides the datasheet information for the HYB18T1G800BC, a member of the HYB18T1G800BF 1-Gbit Double-Data-Rate-Two SDRAM family.

Product Overview

Qimonda

Part number	HYB18T1G800BC
Manufacturer	Qimonda
File Size	3.86 MB
Description	1-Gbit Double-Data-Rate-Two SDRAM
Datasheet	HYB18T1G800BC Datasheet
Additional preview pages of the HYB18T1G800BC datasheet.

Inputs are latched at the cross point of differential clocks (CK rising and CK falling).

All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.

The 1-Gbit Double-data-Rate SDRAM offers the following key features:.
Off-Chip-Driver impedance adjustment (OCD) and On.
1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality.
DRAM organizations with 4, 8 and 16 data in/outputs.
Auto-Precharge operation for read and write bursts.
Double Data Rate architecture: two data transfers per.
Auto-Refresh, Self-Refresh and power saving Powerc.

Other Datasheets by Qimonda

Published: Apr 2, 2009 |