HYB18T1G800BF Overview
1.2 Internet Data Sheet .. HY[B/I]18T1G[40/80/16]0B[C/F](L) 1-Gbit Double-Data-Rate-Two SDRAM HY[B/I]18T1G400B[F/C](L), HY[B/I]18T1G160B[F/C](L), HY[B/I]18T1G800B[F/C](L) Revision History: 1.1 We Listen to Your ments Any information within this document that you feel is wrong, unclear or missing at all?
HYB18T1G800BF Key Features
- Off-Chip-Driver impedance adjustment (OCD) and On- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O Die-Te
- DRAM organizations with 4, 8 and 16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Auto-Refresh, Self-Refresh and power saving Powerclock cycle four internal banks for concurrent operation Down modes
- Programmable CAS Latency: 3, 4, 5 and 6
- Average Refresh Period 7.8 µs at a TCASE lower than
- Programmable Burst Length: 4 and 8 85 °C, 3.9 µs between 85 °C and 95 °C
- Differential clock inputs (CK and CK)
- Programmable self refresh rate via EMRS2 setting
- Programmable partial array refresh via EMRS2 settings
