HYB18TC1G160AF Key Features
- Off-Chip-Driver impedance adjustment (OCD) and On- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O Die-Te
- DRAM organizations with 8, 16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Auto-Refresh, Self-Refresh and power saving PowerDown modes clock cycle four internal banks for concurrent operation
- Average Refresh Period 7.8 µs at a TCASE lower than
- Burst Length: 4 and 8
- Programmable self refresh rate via EMRS2 setting
- Differential clock inputs (CK and CK)
- DCC enabling via EMRS2 setting
- Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read