HYB18TC1G160BF Description
1.21 Page All 14 136 Subjects (major changes since last revision) Adapted internet edition Corrected Table 9: Added Ball B2 and B8 Corrected package outline Editorial changes Previous Revision: 1.2 We Listen to Your ments Any information within this document that you feel is wrong, unclear or missing at all?
HYB18TC1G160BF Key Features
- Off-Chip-Driver impedance adjustment (OCD) and On- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) patible I/O Die-Te
- DRAM organizations with 8 and 16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Auto-Refresh, Self-Refresh and power saving PowerDown modes clock cycle four internal banks for concurrent operation
- Average Refresh Period 7.8 µs at a TCASE lower than
- Programmable CAS Latency: 3, 4, 5 and 6 85 °C, 3.9 µs between 85 °C and 95 °C
- Programmable Burst Length: 4 and 8
- Programmable self refresh rate via EMRS2 setting
- Differential clock inputs (CK and CK)
- Programmable partial array refresh via EMRS2 settings