HYB18TC1G160BF
Overview
- Off-Chip-Driver impedance adjustment (OCD) and On
- 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O Die-Termination (ODT) for better signal quality.
- DRAM organizations with 8 and 16 data in/outputs
- Auto-Precharge operation for read and write bursts
- Double Data Rate architecture: two data transfers per
- Auto-Refresh, Self-Refresh and power saving PowerDown modes clock cycle four internal banks for concurrent operation
- Average Refresh Period 7.8 µs at a TCASE lower than
- Programmable CAS Latency: 3, 4, 5 and 6 85 °C, 3.9 µs between 85 °C and 95 °C
- Programmable Burst Length: 4 and 8
- Programmable self refresh rate via EMRS2 setting
