HYB25D512400DE
Overview
This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics.
- -
- -
- -
- -
- -
- -
- -
- -
- -
- Features
Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions mands entered on each positive CK edge; data and data mask referenced to both edges of DQS Programmable CAS latency: 2, 2.5, 3 and 4 Programmable burst lengths: 2, 4, or 8 Programmable drive strength: normal, weak Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported t RAP = t RCD 7.8 μs Maximum Average Periodic Refresh Interval...
