HD49351BP Datasheet | Renesas

Description The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. HD49351 has deleted the stripe mode, pd_mix mode, and added the 5 - 6 pulse and H_msk2 - 4 as contrasted with HD49335. There are address map and timing generator charts besides this specification. May be contacted to our sales department if examining the details. Functions - - - - - - Correlated double sampling PGA 10-bit ADC Timing generator Operates using only the 3 V voltage Corresponds to switching mode of power consumption and operating frequency 220 m W (Typ), maximum frequency: 36 MHz (HD49351HBP) 150 m W (Typ), maximum frequency: 25 MHz (HD49351BP) - ADC direct input mode - FBGA 65-pin package Features - Suppresses low-frequency noise, which output from CCD by the correlated double sampling. - The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. - High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier. - PGA, pulse timing, standby mode, etc., is achieved via a serial interface. - High precision is provided by a 10-bit-resolution A/D converter. - Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization (wave pattern). It is patented by Renesas. - Timing generator generates the all of pulse which are needed for CCD driving. Rev.1.0, Jul 06, 2004, page 1 of 28 HD49351BP/HBP Pin Arrangement 10 A B C D E F G H J K 9 8 7 6 5 4 3 2 1 32 31 30 29 26 24 22 XV3 XV2 XV1 DVdd3 H2 DVss4 H1 19 17 16 RG VD_i/o HD_i/o 33 34 28 27 25 23 21 20 18 15 XV4 CH1 DVdd4 1/4clk DVss4 1/2clk DVdd4 DVdd3 Reset CLK_in 35 36 CH2 CH3 38 37 XSUB CH4 40 39 SUB_PD SUB_SW 41 42 DVss3 Strob 43 45 Bias AVss 44 46 VRB ADC_in 14 14 13 DVss3 DVss3 DVdd2 12 D9 10 D7 9 D6 7 D4 5 D2 11 D8...