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HD74LV1G126A
Bus Buffer Gate with 3–state Output
REJ03D0072-0700 Rev.7.00 Mar 21, 2008
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Description
The HD74LV1G126A has a bus buffer gate with 3–state output in a 5 pin package. Output is disabled when the associated output enable (OE) input is low. To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor; the minimum value of the resistor is determined by the current sourcing capability of the driver. Low voltage and high-speed operation is suitable for the battery powered products (e.g., notebook computers), and the low power consumption extends the battery life.
Features
• The basic gate function is lined up as Renesas uni logic series.