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HD74LV1GT125A Datasheet Bus Buffer Gate

Manufacturer: Renesas

Overview: HD74LV1GT125A Bus Buffer Gate with 3–state Output / CMOS Logic Level Shifter www.DataSheet4U.net REJ03D0123-0900 Rev.9.

General Description

The HD74LV1GT125A has a bus buffer gate with 3–state output in a 5 pin package.

Output is disabled when the associated output enable (OE) input is high.

To ensure the high impedance state during power up or power down, OE should be connected to VCC through a pull-down resistor;

Key Features

  • The basic gate function is lined up as Renesas uni logic series.
  • Supplied on emboss taping for high-speed automatic mounting.
  • TTL compatible input level. Supply voltage range : 3.0 to 5.5 V Operating temperature range :.
  • 40 to +85°C.
  • Logic-level translate function 3.0 V CMOS logic → 5.0 V CMOS logic (@VCC = 5.0 V) 1.8 V or 2.5 V CMOS logic → 3.3 V CMOS logic (@VCC = 3.3 V).
  • All inputs VIH (Max. ) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO.

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