551MLN Datasheet PDF - Renesas 1 TO 4 CLOCK BUFFER Specs

551MLN - 1 TO 4 CLOCK BUFFER

This page provides the datasheet information for the 551MLN, a member of the 551MLF 1 TO 4 CLOCK BUFFER family.

Datasheet Summary

Description

The ICS551 is a low cost, high-speed single input to four output clock buffer.

Part of IDT’s ClockBlocksTM family, this is our lowest cost, small clock buffer.

See the ICS552-02B for monolithic dual version of the ICS551 in a 20 pin QSOP.

Features

Low skew (250 ps) outputs.
Pb-free packaging.
Low cost clock buffer.
Packaged in 8-pin SOIC.
Input/Output clock frequency up to 160 MHz.
Non-inverting output clock.
Ideal for networking clocks.
Operating Voltages of 3.3 and 5.0 V.
Output Enable mode tri-states outputs.
Advanced, low power CMOS process.
Commercial and industrial temperature versions Block Diagram ICLK Q1 Q2 Q3 Q4 Output Enable I.

Datasheet Details

Part number	551MLN
Manufacturer	Renesas
File Size	310.66 KB
Description	1 TO 4 CLOCK BUFFER
Datasheet	551MLN Datasheet
Additional preview pages of the 551MLN datasheet.

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Full PDF Text Transcription

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1 TO 4 CLOCK BUFFER DATASHEET ICS551 Description The ICS551 is a low cost, high-speed single input to four output clock buffer. Part of IDT’s ClockBlocksTM family, this is our lowest cost, small clock buffer. See the ICS552-02B for monolithic dual version of the ICS551 in a 20 pin QSOP. IDT makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact IDT for all of your clocking needs. Features • Low skew (250 ps) outputs • Pb-free packaging • Low cost clock buffer • Packaged in 8-pin SOIC • Input/Output clock frequency up to 160 MHz • Non-inverting output clock • Ideal for networking clocks • Operating Voltages of 3.3 and 5.

Published: Jan 26, 2021 |