Datasheet Details
| Part number | 551S |
|---|---|
| Manufacturer | Renesas |
| File Size | 1.11 MB |
| Description | Low Skew 1 to 4 Clock Buffer |
| Datasheet |
 551S Datasheet
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General Description
The 551S is a low cost, high-speed single input to four output clock buffer with best in class additive phase jitter of sub 50fsec.
Renesas makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks.
Contact Renesas for all of your clocking needs.
Key Features
- Low additive phase jitter RMS: 50fs.
- Extremely low skew outputs (50ps).
- Low cost clock buffer.
- Packaged in 8-SOIC, 8-TSSOP, and 8-DFN.
- Input/output clock frequency up to 200MHz.
- Non-inverting output clock.
- Ideal for networking clocks.
- Operating voltages: 1.8V to 3.3V.
- Output Enable mode tri-states outputs.
- Advanced, low power CMOS process.
- Extended temperature range (-40°C to +105°C) Block Diagram Q1 Q2 ICLK Q3 Q4 Output Enable Figure 1.