70V26S
Features
- True Dual-Ported memory cells which allow simultaneous reads of the same memory location
- High-speed access
- mercial: 25/35/55ns (max.)
- Low-power operation
- IDT70V26S Active: 300m W (typ.) Standby: 3.3m W (typ.)
- IDT70V26L Active: 300m W (typ.) Standby: 660μW (typ.)
- Separate upper-byte and lower-byte control for multiplexed bus patibility
- IDT70V26 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device
- M/S = VIH for BUSY output flag on Master M/S = VIL for BUSY input on Slave
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- TTL-patible, single 3.3V (±0.3V) power supply
- Available in 84-pin PGA and PLCC
- Green parts available, see ordering information
Functional Block Diagram
R/WL UBL
R/WR UBR
CEL OEL
I/O8L-I/O15L
I/O0L-I/O7L BUSYL(1,2)
A13L A0L
I/O Control
I/O Control
Address Decoder
MEMORY ARRAY
ARBITRATION SEMAPHORE
LOGIC
Address Decoder
SEML
NOTES: 1. (MASTER): BUSY is output; (SLAVE): BUSY is input. 2. BUSY outputs are non-tri-stated push-pull.
M/S
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