8SLVD1204 Datasheet PDF - Renesas LVDS Output Fanout Buffer Specs

8SLVD1204 - LVDS Output Fanout Buffer

Datasheet Summary

Description

The 8SLVD1204 is a high-performance differential LVDS fanout buffer.

The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals.

The 8SLVD1204 is characterized to operate from a 2.5V power supply.

Features

Four low skew, low additive jitter LVDS output pairs.
Two selectable differential clock input pairs.
Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL.
Maximum input clock frequency: 2GHz.
LVCMOS/LVTTL interface levels for the control input select pin.
Output skew: 20ps (maximum).
Propagation delay: 300ps (maximum).
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10k.

Datasheet Details

Part number	8SLVD1204
Manufacturer	Renesas
File Size	768.08 KB
Description	LVDS Output Fanout Buffer
Datasheet	8SLVD1204 Datasheet
Additional preview pages of the 8SLVD1204 datasheet.

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Full PDF Text Transcription

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2:4, LVDS Output Fanout Buffer, 2.5V 8SLVD1204 Datasheet Description The 8SLVD1204 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1204 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1204 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Published: Jan 9, 2025 |