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8SLVD1204 - LVDS Output Fanout Buffer

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Renesas

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8SLVD1204 LVDS Output Fanout Buffer by Renesas - Datasheet Preview — Datasheet preview – 8SLVD1204

Datasheet Details

Part number	8SLVD1204
Manufacturer	Renesas
File Size	768.08 KB
Description	LVDS Output Fanout Buffer
Datasheet	8SLVD1204 Datasheet
Additional preview pages of the 8SLVD1204 datasheet.

Product details

Description

The 8SLVD1204 is a high-performance differential LVDS fanout buffer.

Features

Four low skew, low additive jitter LVDS output pairs.
Two selectable differential clock input pairs.
Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL.
Maximum input clock frequency: 2GHz.
LVCMOS/LVTTL interface levels for the control input select pin.
Output skew: 20ps (maximum).
Propagation delay: 300ps (maximum).
Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10k.

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Published: Jan 9, 2025 |