8SLVD1204-33 Datasheet | IDT

Description The 8SLVD1204-33 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1204-33 is characterized to operate from a 3.3V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1204-33 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise. Features - Four low skew, low additive jitter LVDS output pairs - Two selectable differential clock input pairs - Differential PCLKx, n PCLKx pairs can accept the following differential input levels: LVDS, LVPECL - Maximum input clock frequency: 2GHz - LVCMOS/LVTTL interface levels for the control input select pin - Output skew: 20ps (maximum) - Propagation delay: 310ps (maximum) - L10okw Hazd-d2iti0v Me Hphz:a1s0e0jiftste(rm, Rax Mim S;ufm R)EF = 156.25MHz, VPP = 1V, - Full 3.3V supply voltage - Lead-free (Ro HS 6), 16-Lead VFQFPN packaging - -40°C to 85°C ambient operating temperature Block Diagram PCLK0 n PCLK0 Pulldown Pullup/Pulldown GND GND VDD PCLK1 n PCLK1 Pulldown Pullup/Pulldown GND GND VDD SEL Pullup/Pulldown VREF Reference Voltage Generator 0 1 Q0 n Q0 Q1 n Q1 Q2 n Q2 Q3 n Q3 GND n Q1 SEL Q1 PCLK1 n Q0 n PCLK1 Q0 Pin Assignment 12 11 1 0 Q2 13 9 8 VREF n Q2 14 Q3 15 8XXXXXX 7 n PCLK0 6 PCLK0 n Q3...