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8SLVD1204-33 - LVDS Output Fanout Buffer

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IDT

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8SLVD1204-33 LVDS Output Fanout Buffer by IDT - Datasheet Preview — Datasheet preview – 8SLVD1204-33

Datasheet Details

Part number	8SLVD1204-33
Manufacturer	IDT
File Size	513.19 KB
Description	LVDS Output Fanout Buffer
Datasheet	8SLVD1204-33 Datasheet
Additional preview pages of the 8SLVD1204-33 datasheet.

Product details

Description

The 8SLVD1204-33 is a high-performance differential LVDS fanout buffer.

Features

Four low skew, low additive jitter LVDS output pairs.
Two selectable differential clock input pairs.
Differential PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL.
Maximum input clock frequency: 2GHz.
LVCMOS/LVTTL interface levels for the control input select pin.
Output skew: 20ps (maximum).
Propagation delay: 310ps (maximum).
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Other Datasheets by IDT

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Published: Dec 12, 2016 |