8T33FS6111 Datasheet | Renesas

Low Voltage 2.5V/3.3V Differential LVPECL/HSTL Fanout Buffer DATA SHEET General Description The 8T33FS6111 is a bipolar monolithic differential clock fanout buffer. Designed for most demanding clock distribution systems, the 8T33FS6111 supports various applications that require distribution of precisely aligned differential clock signals. Using Si Ge:C technology and a fully differential architecture, the device offers very low skew outputs and superior digital signal characteristics. Target applications for this clock driver is high performance clock distribution in puting, networking and telemunication systems. The 8T33FS6111 is designed for low skew clock distribution systems and supports clock frequencies up to 2.7GHz. The device accepts two clock sources. The CLKA input can be driven by LVPECL patible signals, the CLKB input accepts HSTL or LVPECL patible signals. The selected input signal is distributed to 10 identical, LVPECL outputs. If VBB is connected to the CLKA input and bypassed to GND by a 10n F capacitor, the 8T33FS6111 can be driven by single-ended LVPECL signals utilizing the VBB bias voltage output. In order to meet the tight skew specification of the device, both outputs of a differential output pair should be terminated, even if only one output is used. In the case where not all ten outputs are used, the output pairs on the same package side as the parts being used on that side should be terminated. The 8T33FS6111 can be operated from a single 3.3V or 2.5V supply. Pin Assignment VCC Q0 n Q0 Q1 n Q1 Q2 n Q2 VCC VCC CLK_SEL 32 31 30 29 28 27 26 25 Q3 n Q3 CLKA 3 22 Q4 n CLKA 4 VBB 5 21 n Q4 20 Q5 CLKB 6 19 n Q5 n CLKB 7 18 Q6 VEE 8 17 n Q6 9 10 11 12 13 14 15 16 Features - 1:10 differential clock distribution - 28ps typical output skew - Fully differential architecture from input to all outputs - Si Ge:C technology supports near-zero output skew - Supports DC to 2.7GHz operation of clock or...