8T39210 Datasheet | Renesas

Crystal or Differential-to-Differential Clock Fanout Buffer 8T39210 Datasheet Description The 8T39210 is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by a single-ended clock. The selected signal is distributed to ten differential outputs that can be configured as LVPECL, LVDS, or HCSL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for a signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply. Block Diagram SMODEA[1:0] Pull-down REF_SEL[1:0] Pull-down CLK0 00 n C LK0 CLK1 01 n C LK1 XTAL_IN OSC 10 or XTAL_OUT SMODEB[1:0] Pull-down OE_SE Pull-down Sync QA0 n QA0 QA1 n QA1 QA2 n QA2 QA3 n QA3 QA4 n QA4 QB0 n QB0 QB1 n QB1 QB2 n QB2 QB3 n QB3 QB4 n QB4 REFOUT Features - Two differential reference clock input pairs - Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL, HSTL, or Single ended - Crystal Input accepts 10MHz to 40MHz Crystal or Single-ended Clock - Maximum Output Frequency - LVPECL - 1.5GHz - LVDS - 1.5GHz - HCSL -...