8T74S208B Description
The 8T74S208B is a high-performance differential LVDS clock divider and fanout buffer. The device is designed for the frequency division and signal fanout of high-frequency, low phase-noise clocks. The 8T74S208B is characterized to operate from a 2.5V power supply.
8T74S208B Key Features
- One differential input reference clock
- Differential pair can accept the following differential input
- Integrated input termination resistors
- Eight LVDS outputs
- Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
- Maximum input clock frequency: 1GHz
- LVCMOS interface levels for the control inputs
- Individual output enabled/ disabled by I2C interface
- Output skew: 45ps (maximum)
- Output rise/fall times: 370ps (maximum)