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8V79S680 Datasheet JESD204B Compliant Fanout Buffer/Divider

Manufacturer: Renesas

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General Description

The 8V79S680 is a fully integrated, clock and SYSREF signal fanout buffer for JESD204B applications.

It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B subclass 0, 1, and 2 compliance.

The main function of the device is the distribution and fanout of high-frequency clocks and low-frequency system reference signals generated by a JESB204B clock generator such as the IDT 8V19N480, extending its fanout capabilities and providing additional phase-delay.

Overview

JESD204B Compliant Fanout Buffer and Divider 8V79S680 Datasheet.

Key Features

  • Supports high-speed, low phase noise converter clocks.
  • Distribution, fanout, phase-delay of clock and SYSREF signals.
  • Very low output noise floor: -158.8dBc/Hz noise floor (245.76MHz).
  • Supports clock frequencies up to 3GHz, including clock output frequencies of 983.04MHz, 491.52MHz, 245.76MHz, and 122.88MHz.
  • 4 output channels with a total of 16 differential outputs, organized in:.
  • 8 dedicated clock outputs.
  • 8 outputs configurable as SYSREF outputs with.

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