8V79S683 Description
The 8V79S683 is a fully integrated, clock and SYSREF signal fanout buffer for JESD204B/C applications. It is designed as a high-performance clock and converter synchronization solution for wireless base station radio equipment boards with JESD204B/C subclass 0, 1, and 2 pliance. The main function of the device is the distribution and fanout of high-frequency clocks and low-frequency system reference signals...
8V79S683 Key Features
- Distribution, fanout, phase-delay of clock and SYSREF signals
- Very low output noise floor: -158.8dBc/Hz noise floor
- Supports clock frequencies up to 3GHz, including clock output
- Four output channels with a total of 16 differential outputs
- Each channel contains frequency dividers and clock phase delay circuits
- Phase alignment mode across multiple buffers with any frequency divider setting
- Flexible differential outputs (LVDS/LVPECL/amplitude configurable)
- Configuration through 3-wire SPI interface
- Supply voltage
- 3.3V core and signal I/O