9DB1933 Datasheet PDF - Renesas Nineteen Output Differential Buffer Specs

9DB1933 - Nineteen Output Differential Buffer

Datasheet Summary

Description

The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1.

The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator.

Features

19 - 0.7V current mode differential HCSL output pairs Features/Benefits.
8 Selectable SMBus Addresses/Mulitple devices can share the same SMBus Segment.
11 dedicated and 3 group OE# pins/Hardware control of the outputs.
PLL or bypass mode/PLL can dejitter incoming clock.
Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's.
Spread Spectrum Compatible/tracks spreading input clock for low EMI.
SMBus Interface/unused.

Datasheet Details

Part number	9DB1933
Manufacturer	Renesas
File Size	294.78 KB
Description	Nineteen Output Differential Buffer
Datasheet	9DB1933 Datasheet
Additional preview pages of the 9DB1933 datasheet.

📁 Similar Datasheet

9DB1933 - Nineteen Output Differential Buffer (IDT)

9DB1904B - 19 Output Differential Buffer (IDT)

9DB106 - Six Output Differential Buffer (IDT)

9DB1200C - Twelve Output Differential Buffer (IDT)

9DB1233 - Twelve Output Differential Buffer (IDT)

9DB233 - Two Output Differential Buffer (IDT)

9DB306 - PCI Express Jitter Attenuator (IDT)

9DB423B - Four Output Differential Buffer (IDT)

9DB433 - FOUR OUTPUT DIFFERENTIAL BUFFER (IDT)

9DB633 - Six Output Differential Buffer (IDT)

Full PDF Text Transcription

Click to expand full text

Nineteen Output Differential Buffer for PCIe Gen3 DATASHEET 9DB1933 Recommended Application 19 output PCIe Gen3 zero-delay/fanout buffer General Description The 9DB1933 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB1933 is driven by a differential SRC output pair from an IDT 932S421, 932SQ420, or equivalent, main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. Output Features • 19 - 0.

Published: Dec 14, 2020 |