Renesas Electronics 9DB633
The 9DB633 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB633 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking.| Part No. | 9DB633 |
|---|---|
| Datasheet | 9DB633 Download |
| Manufacturer |  Renesas Electronics |
| Description | Differential Buffer |
| Buy | Stock & Price |
GENERAL DESCRIPTION
: An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (OE#) pins make the 9DB633 suitable for Express Card applications. Key Specifications:● Cycle-to-cycle jitter < 50 ps
● Output-to-output skew < 50 ps
● PCIe Gen3 phase jitter < 1.0ps RMS Block Diagram
FEATURES
/Benefits:● OE# pins/Suitable for Express Card applications
● PLL or bypass mode/PLL can dejitter incoming clock
● Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
● Spread Spectrum Compatible/tracks spreading input clock for low EMI
● SMBus Interface/unused outputs can be disabled Output
FEATURES
:● 6 - 0.7V current mode differential HCSL output pairs OE1# OE4# SRC_IN SRC_IN# PLL_BW SMBDAT SMBCLK SPREAD COMPATIBLE PLL CONTROL LOGIC DIF1 DIF4 DIF(0,2,3,5) IREF IDT® Six Output Differential Buffer for PCIe Gen3 1 1668F—10/20/16 9DB633 Six Output Differential Buffer for PCIe Gen3 Pin Configuration PLL_BW 1 SRC_IN 2 SRC_IN# 3 vOE1# 4 DIF_0 5 DIF_...
