9DB836 Description
The 9DB836 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen1 3 in zero-delay mode and PCIe Gen1 4 in fanout mode. The 9DB836 is a pin-patible upgrade to the 9DB833 and 9DB834 with a Safe Power Sequence (SPS) clock input.
9DB836 Key Features
- Eight 0.7V current-mode differential HCSL output pairs
- Supports zero delay buffer (ZDB) mode and fanout mode
- Selectable bandwidth for zero delay mode
- 50-110 MHz operation in PLL mode
- 5-166 MHz operation in Bypass mode
- SPS internal receiver bias network keeps input clock parked when input is floating
- Supports both 85Ω and 100Ω output impedance with appropriate resistor selection
- OE# pins default to controlling outputs
- PLL or Bypass mode; PLL can dejitter ining clock
- Spread spectrum patible