9DBL0651C Description
The buffers support PCIe Gen1 through Gen6. PCIe Clocking Architectures mon Clocked (CC) Independent Reference (IR) with and without spread spectrum (SRIS, SRNS) Typical Applications PCIe Riser Cards nVME Storage Networking Accelerators Industrial Control/Embedded Key Specifications Additive PCIe Gen6 CC jitter < 18fs RMS (fanout mode) PCIe Gen6 CC jitter < 100fs RMS (High-BW ZDB Mode).
9DBL0651C Key Features
- 2 to 8 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
- 9DBL0x4x devices provide integrated 100Ω terminations
- 9DBL0x5x devices provide integrated 85Ω terminations
- See AN-891 for easy coupling to other logic families
- Spread-spectrum patible
- Dedicated OE# pin for each output
- 1MHz to 200MHz operation in fan-out mode
- 3 selectable SMBus addresses
- Extensive SMBus-selectable features allow
- SMBus interface not required for device operation