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9FGL0641D Datasheet

3.3v Pcie Gen1-6 Clock Generator

Manufacturer: Renesas

This datasheet includes multiple variants, all published together in a single manufacturer document.

9FGL0641D Overview

There are 2, 4, 6, and 8 outputs versions available and each differential output has a dedicated OE# pin supporting PCIe CLKREQ# functionality. PCIe Clocking Architectures mon Clocked (CC) Independent Reference (IR) with and without spread spectrum (SRIS, SRNS) Applications Servers/High-Performance puting nVME Storage Networking Accelerators Industrial Control Output.

9FGL0641D Key Features

  • 2, 4, 6, or 8 100MHz PCIe output pairs
  • One 3.3V LVCMOS REF output with Wake-On
  • See AN-891 for easy AC-coupling to other logic
  • 40fs RMS typical jitter (PCIe Gen6 CC)
  • < 50ps cycle-to-cycle jitter on differential outputs
  • < 50ps output-to-output skew on differential outputs
  • ±0ppm synthesis error on differential outputs
  • Integrated terminations for 100Ω and 85Ω systems save 4 resistors per output
  • 112-206 mW typical power consumption (at 3.3V)
  • VDDIO rail allows 35% power savings at optional

9FGL0641D Distributor