HD74HC137 Description
The HD74HC137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains high no address changes will be recognized.
HD74HC137 Key Features
- High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)
- High Output Current: Fanout of 10 LSTTL Loads
- Wide Operating Voltage: VCC = 2 V to 6 V
- Low Input Current: 1 µA max
- Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta
HD74HC137 Applications
- High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)