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HD74HC533 - Octal D-type Transparent Latches

Download the HD74HC533 datasheet PDF. This datasheet also covers the HD74HC373 variant, as both devices belong to the same octal d-type transparent latches family and are provided as variant models within a single manufacturer datasheet.

General Description

When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs.

When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again.

Key Features

  • High Speed Operation: tpd (D to Q) = 16 ns typ (CL = 50 pF).
  • High Output Current: Fanout of 15 LSTTL Loads.
  • Wide Operating Voltage: VCC = 2 to 6 V.
  • Low Input Current: 1 µA max.
  • Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C).
  • Ordering Information Part Name Package Type Package Code (Previous Code) HD74HC373P HD74HC533P DILP-20 pin PRDP0020AC-B (DP-20NEV) HD74HC373FPEL HD74HC533FPEL SOP-20 pin (JEITA) PRSP0020DD-.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (HD74HC373-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number HD74HC533
Manufacturer Renesas
File Size 134.47 KB
Description Octal D-type Transparent Latches
Datasheet download datasheet HD74HC533 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
HD74HC373, HD74HC533 Octal D-type Transparent Latches (with 3-state outputs) Octal D-type Transparent Latches (with inverted 3-state outputs) REJ03D0619-0300 Rev.3.00 Mar 25, 2009 Description When the latch enable input is high, the Q outputs of HD74HC373 will follow the D inputs and the Q outputs of HD74HC533 will follow the inversion of the D inputs. When the latch enable goes low, data at the D inputs will be retained at the outputs until latch enable returns high again. When a high logic level is applied to the output control input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements.