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ICS252BI09L - VCXO Jitter Attenuator & Synchronous Multiplier

General Description

The 813N252I-09 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation.

The device contains two internal frequency multiplication stages that are cascaded in series.

Key Features

  • Two LVPECL output pairs Each output supports independent frequency selection at 25MHz, 125MHz, 156.25MHz and 312.5MHz.
  • Two differential inputs support the following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL.
  • Accepts input frequencies from 8kHz to 155.52MHz including 8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz, 125MHz and 155.52MHz.
  • Attenuates the phase jitter of the input clock by using a low-cost pullable fundamental mode VCXO crystal.
  • V.

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Datasheet Details

Part number ICS252BI09L
Manufacturer Renesas
File Size 863.00 KB
Description VCXO Jitter Attenuator & Synchronous Multiplier
Datasheet download datasheet ICS252BI09L Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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VFeCmXOtoCJiltotcekr®AMttuelntuipaltioerr & 813N252I-09 Datasheet General Description The 813N252I-09 is a PLL based synchronous multiplier that is optimized for PDH or SONET to Ethernet clock jitter attenuation and frequency translation. The device contains two internal frequency multiplication stages that are cascaded in series. The first stage is a VCXO PLL that is optimized to provide reference clock jitter attenuation. The second stage is a FemtoClock™frequency multiplier that provides the low jitter, high frequency Ethernet output clock that easily meets Gigabit and 10 Gigabit Ethernet jitter requirements. Pre-divider and output divider multiplication ratios are selected using device selection control pins.