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ICS527-04 - Clock Slicer

General Description

The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew.

The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock.

Key Features

  • Packaged as 28-pin SSOP (150 mil body).
  • Synchronizes fractional clocks rising edges.
  • CMOS in to PECL out.
  • PECL in to PECL out.
  • Pin selectable dividers.
  • Zero input to output skew.
  • User determines the output frequency - no software needed.
  • Slices frequency or period.
  • Input clock frequency of 1.5 MHz - 200 MHz.
  • Output clock frequencies up to 160 MHz.
  • Very low jitter.
  • Duty cycle of 45/55.

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📁 Similar Datasheet

Part Number Description Manufacturer
ICS527-04 Clock Slicer User Configurable PECL input Zero Delay Buffer Integrated Circuit Systems
ICS527-01 User Configurable Zero Delay Buffer Integrated Circuit Systems
ICS527-02 Clock Slicer User Configurable PECL Input Zero Delay Buffer Integrated Circuit Systems
ICS527-03 Clock Slicer User Configurable PECL Output Zero Delay Buffer Integrated Circuit Systems
ICS524 LOW SKEW 1 TO 4 CLOCK BUFFER Integrated Device Technology

Other Datasheets by Renesas

Part Number Description
ICS527-02 CLOCK SLICER USER CONFIGURABLE PECL INPUT ZERO DELAY BUFFER
ICS527-03 CLOCK SLICER USER CONFIGURABLE PECL OUTPUT ZDB
ICS524 LOW SKEW 1 TO 4 CLOCK BUFFER
ICS501 PLL CLOCK MULTIPLIER
ICS501A PLL CLOCK MULTIPLIER

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CLOCK SLICER USER CONFIGURABLE PECL INPUT ZDB DATASHEET ICS527-04 Description The ICS527-04 Clock Slicer is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz. The ICS527-04 aligns rising edges on PECLIN with FBPECL at a ratio determined by the reference and feedback dividers. For other PECL output clocks, see the ICS507-01, ICS525-03, or the MK3707. For PECL in and CMOS out, see the ICS527-02.