ICS97U8770 Overview
Package options include a plastic 52-ballVFBGA and a 40-pin MLF. ICS97U870 is a zero delay buffer that distributes a differential clock input pair(CLK_INT, CLK_INC) to ten differential pair of clock outputs(CLKT[0:9], CLKC[0:91) and one differential pair feedback clock outputs(FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks(CLK_INT, CLK_INC), the feedback clocks(FB_INT, FB_INC), the LVCMOS...