IDT2309A Description
The IDT2309A is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the ining clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309A is a 16-pin version of the IDT2305A.
IDT2309A Key Features
- Phase-Lock Loop Clock Distribution
- 10MHz to 133MHz operating frequency
- Separate output enable for each output bank
- Output Skew < 250ps
- Low jitter <200 ps cycle-to-cycle
- IDT2309A-1 for Standard Drive
- IDT2309A-1H for High Drive
- No external RC network required
- Operates at 3.3V VDD
- Available in SOIC and TSSOP packages