IDT723666 Datasheet | Renesas

CMOS TRIPLE BUS Sync FIFOTM WITH BUS-MATCHING IDT723656 2,048 x 36 x 2 4,096 x 36 x 2 IDT723676 8,192 x 36 x 2 OBSOLETE PARTS Features - Serial or parallel programming of partial flags - Memory storage capacity: IDT723656 - 2,048 x 36 x 2 - Big- or Little-Endian format for word and byte bus sizes - Loopback mode on Port A - 4,096 x 36 x 2 - Retransmit Capability IDT723676 - 8,192 x 36 x 2 - Master Reset clears data and configures FIFO, Partial Reset - Clock frequencies up to 83 MHz (8ns access time) - Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives clears data but retains configuration settings - Mailbox bypass registers for each FIFO - Free-running CLKA, CLKB and CLKC may be asynchronous or and Port B transmits) coincident (simultaneous reading and writing of data on a single - 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C - Select IDT Standard timing (using EFA , EFB , FFA , and FFC flag S R functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRC flag functions) - Programmable Almost-Empty and Almost-Full flags; each has R F five default offsets (8, 16, 64, 256 and 1024) clock edge is permitted) - Auto power down minimizes power dissipation - Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) - Pin patible to the lower density parts, IDT723626/3636/3646...