MC100ES6056 - ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer

Renesas

General Description

Pin Function D0a D1a ECL Input Data a D0a D1a ECL Input Data a Invert D0b D1b ECL Input Data b D0b D1b ECL Input Data b Invert SEL0 SEL1

ECL Indiv.

ECL Common Sel

Key Features

both individual and common select inputs to address both data path and random logic.

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MC100ES6056 ecl/lvpecl/lvds dual differential 2:1 multiplexer by Renesas - Datasheet Preview

Datasheet Details

Part number	MC100ES6056
Manufacturer	Renesas
File Size	597.28 KB
Description	ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer
Datasheet	MC100ES6056 Datasheet

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Full PDF Text Transcription (Reference)

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2.5V, 3.3V ECL/LVPECL/LVDS Dual Differential 2:1 Multiplexer NRND – Not Recommend for New Designs Product Discontinuance Notice – Last Time Buy Expires on (12/23/2013) MC100ES6056 NRND DATASHEET The MC100ES6056 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. Multiple VBB pins are provided. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.