R1Q2A7209ABB Overview
It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit configuration.
R1Q2A7209ABB Key Features
- 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
- Fast clock cycle time for high bandwidth
- Two input clocks (K and /K) for precise DDR timing at clock rising edges only
- Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches
- Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
- Clock-stop capability with s restart
- Separate independent read and write data ports with concurrent transactions
- 100% bus utilization DDR read and write operation
- HSTL I/O
- User programmable output impedance
R1Q2A7209ABB Applications
- 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
- Fast clock cycle time for high bandwidth
- Two input clocks (K and /K) for precise DDR timing at clock rising edges only
- Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches
- Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems
- Clock-stop capability with s restart
- Separate independent read and write data ports with concurrent transactions