R5F52106ADFN Overview
Preliminary Data Sheet Specifications in this document are tentative and subject to change. RX210 Group Renesas MCUs 50-MHz 32-bit RX MCUs, 78 DMIPS, up to 512-KB flash memory, 12-bit AD, 10-bit DA, ELC, MPC, RTC, up to 9 ms interfaces; incorporating functions for IEC60730 pliance R01DS0041EJ0050 Rev.0.50 Apr 15, 2011.
R5F52106ADFN Key Features
- 32-bit RX CPU core
- Max. operating frequency: 50 MHz Capable of 78 DMIPS in operation at 50 MHz
- Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations
- Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)
- Fast interrupt
- CISC Harvard architecture with 5-stage pipeline
- Variable-length instructions, ultra-pact code
- On-chip debugging circuit
- Low-power design and architecture
- Operation from a single 1.62- to 5.5-V supply