R5F52201BDFM Datasheet PDF - Renesas 32-MHz 32-bit RX MCUs Specs

R5F52201BDFM - 32-MHz 32-bit RX MCUs

This page provides the datasheet information for the R5F52201BDFM, a member of the R5F52206BDFP 32-MHz 32-bit RX MCUs family.

Datasheet Summary

Description

Maximum operating frequency: 32 MHz 32-bit RX CPU Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register General purpose: Sixteen 32-bit registers Control: Eight 32-bit registers Accumulator: One

Features

32-bit RX CPU core.
Max. operating frequency: 32 MHz.
Capable of 49 DMIPS in operation at 32 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with 5-stage pipeline.
Variable-length instructions, ultra-compact code.
On-chip debugging circuit.

Datasheet Details

Part number	R5F52201BDFM
Manufacturer	Renesas
File Size	1.00 MB
Description	32-MHz 32-bit RX MCUs
Datasheet	R5F52201BDFM Datasheet
Additional preview pages of the R5F52201BDFM datasheet.

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Full PDF Text Transcription

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Preliminary Datasheet Specifications in this document are tentative and subject to change. RX220 Group Renesas MCUs 32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, RTC, up to 7 comms channels; incorporating functions for IEC60730 compliance R01DS0130EJ0051 Rev.0.51 May 24, 2012 Features ■ 32-bit RX CPU core  Max.

Published: Jun 3, 2012 |