R5F52201BGFL Datasheet PDF - Renesas 32-MHz 32-bit RX MCUs Specs

R5F52201BGFL - 32-MHz 32-bit RX MCUs

This page provides the datasheet information for the R5F52201BGFL, a member of the R5F52206BDFP 32-MHz 32-bit RX MCUs family.

Datasheet Summary

Features

32-bit RX CPU core.
Max. operating frequency: 32 MHz.
Capable of 49 DMIPS in operation at 32 MHz.
Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations.
Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle).
Fast interrupt.
CISC Harvard architecture with 5-stage pipeline.
Variable-length instructions, ultra-compact code.
On-chip debugging circuit.

Datasheet Details

Part number	R5F52201BGFL
Manufacturer	Renesas
File Size	1.00 MB
Description	32-MHz 32-bit RX MCUs
Datasheet	R5F52201BGFL Datasheet
Additional preview pages of the R5F52201BGFL datasheet.

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Full PDF Text Transcription

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Datasheet RX220 Group Renesas MCUs 32-MHz 32-bit RX MCUs, 49 DMIPS, up to 256-KB flash memory, 12-bit A/D, ELC, MPC, IrDA, RTC, up to 7 comms channels; incorporating functions for IEC60730 compliance R01DS0130EJ0110 Rev.1.10 Dec 20, 2013 Features ■ 32-bit RX CPU core  Max. operating frequency: 32 MHz  Capable of 49 DMIPS in operation at 32 MHz  Accumulator handles 64-bit results (for a single instruction) from 32- × 32-bit operations  Multiplication and division unit handles 32- × 32-bit operations (multiplication instructions take one CPU clock cycle)  Fast interrupt  CISC Harvard architecture with 5-stage pipeline  Variable-length instructions, ultra-compact code  On-chip debugging circuit ■ Low-power design and architecture  Operation from a single 1.62-V to 5.

Published: Mar 26, 2019 |