R5F52315ADFL - MCU

This page provides the datasheet information for the R5F52315ADFL, a member of the R5F52318ADLA MCU family.

Product Overview

Renesas

Part number	R5F52315ADFL
Manufacturer	Renesas
File Size	3.78 MB
Description	MCU
Datasheet	R5F52315ADFL Datasheet
Additional preview pages of the R5F52315ADFL datasheet.

32-bit RXv2 CPU core.
Max. operating frequency: 54 MHz Capable of 88.56 DMIPS in operation at 54 MHz.
Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply-subtract instructions supported.
Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754).
Divider (fastest instruction execution takes two CPU clock cycles).
Fast interrupt.
CISC Harvard architecture with 5-stage pipeline.
Variable-length instructi.

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Published: Aug 12, 2020 |