R5F52317BDFL Datasheet | Renesas

Features - 32-bit RXv2 CPU core - Max. operating frequency: 54 MHz Capable of 88.56 DMIPS in operation at 54 MHz - Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply-subtract instructions supported - Built-in FPU: 32-bit single-precision floating point (pliant to IEEE754) - Divider (fastest instruction execution takes two CPU clock cycles) - Fast interrupt - CISC Harvard architecture with 5-stage pipeline - Variable-length instructions, ultra-pact code - On-chip debugging circuit - Memory protection unit (MPU) supported - Low power design and architecture - Operation from a single 1.8-V to 5.5-V supply - RTC capable of operating on the battery backup power supply - Three low power consumption modes - Low power timer (LPT) that operates during the software standby state - On-chip flash memory for code - 128- to 512-Kbyte capacities - On-board or off-board user programming - Programmable at 1.8 V - For instructions and operands - On-chip data flash memory - 8 Kbytes (1,000,000 program/erase cycles (typ.)) - BGO (Background Operation) - On-chip SRAM, no wait states - 32- to 64-Kbyte size capacities - Data transfer functions - DMAC: Incorporates four channels - DTC: Four transfer modes - ELC - Module operation can be initiated by event signals without using interrupts. - Linked operation between modules is possible while the CPU is sleeping. - Reset and supply management - Eight types of reset, including the power-on reset (POR) - Low voltage detection (LVD) with voltage settings - Clock functions - Main clock oscillator frequency: 1 to 20 MHz - External clock input frequency: Up to 20 MHz - Sub-clock oscillator frequency: 32.768 k Hz - PLL circuit input: 4 MHz to 12.5...