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R5F523T3ADFD - MCU

This page provides the datasheet information for the R5F523T3ADFD, a member of the R5F523T5ADFL MCU family.

Datasheet Summary

Description

CPU CPU Maximum operating frequency: 40 MHz 32-bit RX CPU (RX v2) Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 7

Features

  • 32-bit RX CPU core.
  • Max. operating frequency: 40 MHz Capable of 65.6 DMIPS in operation at 40 MHz.
  • Enhanced DSP: 32-bit multiply-accumulate and 16-bit multiply-subtract instructions supported.
  • Built-in FPU: 32-bit single-precision floating point (compliant to IEEE754).
  • Divider (fastest instruction execution takes two CPU clock cycles).
  • Fast interrupt.
  • CISC Harvard architecture with 5-stage pipeline.
  • Variable-length instructions, ultra-compact code.
  • O.

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Datasheet preview – R5F523T3ADFD

Datasheet Details

Part number R5F523T3ADFD
Manufacturer Renesas
File Size 1.02 MB
Description MCU
Datasheet download datasheet R5F523T3ADFD Datasheet
Additional preview pages of the R5F523T3ADFD datasheet.

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Full PDF Text Transcription

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Datasheet RX23T Group Renesas MCUs R01DS0248EJ0110 Rev.1.10 Jan 13, 2016 40-MHz 32-bit RX MCUs, built-in FPU, 65.6 DMIPS, 12-bit ADC (equipped with three S/H circuits, double data registers, and comparator) 40MHz PWM (three-phase complementary output × 2ch) Features ■ 32-bit RX CPU core  Max. operating frequency: 40 MHz Capable of 65.
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