R7F100GAJ - MCU

This page provides the datasheet information for the R7F100GAJ, a member of the R7F100GFN MCU family.

Features

Ultra-low power consumption technology.
VDD = single power supply voltage of 1.6 to 5.5 V.
HALT mode.
STOP mode High-speed wakeup from the STOP mode is possible.
SNOOZE mode RL78 CPU core.
CISC architecture with 3-stage pipeline.
Minimum instruction execution time: Can be changed from high speed (0.03125 µs @ 32 MHz operation with the high-speed on-chip oscillator clock) to ultra-low speed (30.5 µs @ 32.768 kHz operation with the subsystem c.

Renesas

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Datasheet Details

Part number	R7F100GAJ
Manufacturer	Renesas
File Size	1.98 MB
Description	MCU
Datasheet	R7F100GAJ Datasheet
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Datasheet RL78/G23 RENESAS MCU R01DS0395EJ0130 Rev.1.30 Jan 31, 2024 True low-power platform, 41-µA/MHz operating current, 210-nA data retention current for 4 KB of RAM, up to 768-KB code flash memory and 48-KB RAM, capacitive sensing unit, from 30 to 128 pins, 1.6-5.5 V 1. Outline 1.1 Features Ultra-low power consumption technology • VDD = single power supply voltage of 1.6 to 5.5 V • HALT mode • STOP mode High-speed wakeup from the STOP mode is possible. • SNOOZE mode RL78 CPU core • CISC architecture with 3-stage pipeline • Minimum instruction execution time: Can be changed from high speed (0.03125 µs @ 32 MHz operation with the high-speed on-chip oscillator clock) to ultra-low speed (30.5 µs @ 32.

Published: Jan 18, 2025 |