R9A07G084M08GBG
Overview
- On-chip 32-bit Arm Cortex-R52 processor
- High-speed realtime control with operating frequency of 200/400 MHz
- On-chip Single 32-bit Arm Cortex-R52 (revision r1p2)
- Tightly coupled memory (TCM) with ECC - CPU0: 128 KB/128 KB
- Instruction cache/data cache with ECC - CPU0: 16 KB per cache
- High-speed interrupt
- The FPU supports addition, subtraction, multiplication, division, multiply-and-accumulate, and square-root operations at singleprecision and double-precision.
- The NEON, Advanced SIMD, supports integer or single precision results.
- Harvard architecture with 8-stage pipeline
- Supports the memory protection unit (MPU)
