Datasheet4U Logo Datasheet4U.com

RC21012A - VersaClock 7 Programmable Clock Generator

Download the RC21012A datasheet PDF. This datasheet also covers the RC21008A variant, as both devices belong to the same versaclock 7 programmable clock generator family and are provided as variant models within a single manufacturer datasheet.

General Description

RCxx012A 7 1.3 Pin Assignments RCxx008A

.

.

.

RCxx008A

Key Features

  • 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz).
  • PCIe® Gen6 Common Clock (CC) 27fs RMS.
  • PCIe SRIS and SRNS support.
  • 1kHz to 650MHz LVDS/LP-HCSL outputs 008 A/012A XIN_REFIN X XOUT_REFINb O CLKIN0_GPI0 CLKIN0b_GPI1 CLKIN1_GPI2 CLKIN1b_GPI3 APL L GPIO[4:0] SCL_SCLK SDA_nCS GPIO Ser ial Por t OTP Use r Cfgs Registe rs A. IOD0 is n/a on 008 devices MUX MUX.
  • 1kHz to 200MHz LVCMOS outputs.
  • Simple AC-coupling to LVPECL and CML.
  • LP-HCSL integrates 100 o.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (RC21008A-Renesas.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number RC21012A
Manufacturer Renesas
File Size 1.90 MB
Description VersaClock 7 Programmable Clock Generator
Datasheet download datasheet RC21012A Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
RC210xxA VersaClock 7 Programmable Clock Generator Family Datasheet The RC210xxA (RC21012A and RC21008A) are high-performance programmable clock generators for compute, data-communications, and industrial applications. Applications ▪ High-performance computing ▪ Data center accelerators ▪ Enterprise storage ▪ Switches and routers ▪ Industrial Features ▪ 169fs RMS phase jitter (10kHz - 20MHz, 156.25MHz) ▪ PCIe® Gen6 Common Clock (CC) 27fs RMS ▪ PCIe SRIS and SRNS support ▪ 1kHz to 650MHz LVDS/LP-HCSL outputs 008 A/012A XIN_REFIN X XOUT_REFINb O CLKIN0_GPI0 CLKIN0b_GPI1 CLKIN1_GPI2 CLKIN1b_GPI3 APL L GPIO[4:0] SCL_SCLK SDA_nCS GPIO Ser ial Por t OTP Use r Cfgs Registe rs A.